TAGGED: pdn, power-integrity, signal-integrity
-
-
October 30, 2024 at 3:46 pmspdpwSubscriber
Hi,
I want to extract the loop inductance of a power/ground plane pair with vias stitched between them. There are 2 power vias and 7 ground vias in between 4in*4in power plane pair. I created the antipad for the vias and assigned the sources in the via faces. Moreover, the plane face is assigned as the sink. I reduced my sources on power vias by connecting them in parallel. Similarly, this is done for the ground sources as well. Then, the sink of power plane is connected to the source of the ground plane in series. This way total loop inductance is extracted. I don't know if I have done this correctly or not. Please suggest if there is any mistake while assigning the source and sink to the nets.Â
Thanks :)
-
- You must be logged in to reply to this topic.
- Polarization and Angle of Incidence Scan with Floquet ports in ANSYS HFSS
- SLURM integration
- How to create Lumped RLC in HFSS to match Circuit? (Simulate load as Lumped RLC)
- CPW resonant frequency HFSS Simulation
- EMA3D Current Source Problem
- Zo when applying bulk conductivity to the silicon substrate of finite-ground CPW
- Simplorer link to Maxwell transient
- Help on calculating port impedance Zpv using Field calculator under HFSS please
- Question for Maxwell
-
781
-
407
-
265
-
201
-
162
© 2024 Copyright ANSYS, Inc. All rights reserved.