Extracting parasitics out of a PCB layout or cut out of the board

- April 10, 2020 at 10:17 pm
  
  Marsha
  Subscriber
  
  Hi all,
  
  I'm new in using Ansys and going to extract parasitic elements from a cut out of a PCB layout.
  
  I've imported my PCB layout from Cadence PCB editor into SIWave and trying to make a cut out of my board into Q3D extractor and then extract the parasitic of the desired traces.
  
  First, While making a cut out of my board, sometimes I am not able to draw geometry (draw a polygon extent), before importing into Q3D. It seems that this is deactivated for some reason. However, I was able to do that before and I have the license on my laptop.
  
  Second, After importing into Q3D extractor, since it takes a long time for Ansys to make the mesh and solve the problem, I'm going to cut the board to small pieces and make the simulation locally. I know that I need to assign the source and sink before running the simulation, but I do not know when I make a cut out of the PCB board, where it should be assigned as a source and a sink. I mean basically, the power is coming from or out of a connector. but, it seems that I'm not able to assign the source into a pin. Rather, I should assign the source or sink into a sheet or ... .
  
  Third, After completing the simulation, how can I find the RL parasitic for a specific trace such as ground. considering my ground trace is a long and thick trace coming from the left side to the right side of the board, how can I specify for the software to find parasitic RL of which part of the trace is the target.
  
  I really appreciate your help cause I've stuck for days to make this simulation