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Time step not converging in Transient simulation with RPI Wall boiling

- October 11, 2023 at 6:22 am
  
  Manish Patel
  Subscriber
  
  I am trying to simulate subcooled flow boiling in horizontal channel with Non-equilibrium RPI wall boiling model. It is transient simulation with Implicit scheme. Steady state simulation are not giving the true results so that scenario is already discarded. I have already performed grid independency and now trying to do time step converging for transient simulation. Started with time step of 5E-02 and reduced upto 1E-05. But, the results keep changing everytime. The results have shown to match when time step is arounf 5E-02. With smaller time step, I am not even seeing boiling starting.
  So, please help me how time step convergence can be achieved?
  The models and schemes are listed below.
- October 13, 2023 at 10:20 am
  
  Prashanth
  Ansys Employee
  
  Hello, what is the y-plus values near the walls of interest when you change the timesteps? Also, which Fluent release are you using?
- October 17, 2023 at 7:39 am
  
  Manish Patel
  Subscriber
  
  The y+ valus is 30. I am using Ansys 2021 R1.
- October 23, 2023 at 11:08 am
  
  Manish Patel
  Subscriber
  
  Can I get some input to solve the problem i am facing?

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