Learning Forum

[ldengaq]

I want to design a interconnect structure in semiconductor metal layer and know the new structure RLGC behaviour in circuit response. Interconnect structure generally have a source come from transistor output and multiple sink terminal for outside electrical connect. Unfortunately, I found that in Q3D extractor, I can't  define one source and two sink, which can not meet my simulation requirment. If I define two source and one sink, and then connect the sink with transistor output and source with other outside electrical connect, I found that the spice model isn't accurate. I would like to know if there are any methods that can define a one-input and two-output RLGC model for circuit simulation. Thank you very much.

[ssano]

Thank you for your inquiry.
As you pointed out, it is not possible to define two Sinks on one net.
This is because the current path cannot be uniquely determined.
As you understand, we define two Sources and one Sink to output the equivalent circuit.
When excluding Capacitance, if only Resistance and Inductance are in the circuit, the analysis results should be the same regardless of which point is set as the Sink.