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[spdpw]

Hi,

I want to extract the loop inductance of a power/ground plane pair with vias stitched between them. There are 2 power vias and 7 ground vias in between 4in*4in power plane pair. I created the antipad for the vias and assigned the sources in the via faces. Moreover, the plane face is assigned as the sink. I reduced my sources on power vias by connecting them in parallel. Similarly, this is done for the ground sources as well. Then, the sink of power plane is connected to the source of the ground plane in series. This way total loop inductance is extracted. I don't know if I have done this correctly or not. Please suggest if there is any mistake while assigning the source and sink to the nets.

 

Thanks :)

[Sriparna]

Hi,

Thanks for asking the question in Ansys Learning Forum.

Usually we do source and sink definition for PWR and GND net on both VRM and Microcontroller side in Q3D. So there will be one source and sink for PWR net and another source and sink for GND net. Then we can consider Return path Reduce matrix operation to evaluate Loop Inductance of the PWR plane. There we define the GND net as the Return path.