Spurious Frequency Synthesis — Lesson 4

This lesson covers the spurious frequency synthesis. The lesson explains the importance of the loop bandwidth and its relation to the reference frequency. It also discusses the impact of glitches on the control voltage and how to reduce these tones. The lesson further explores the concept of dividing a frequency by non-integers and the implications of this on the loop bandwidth and phase noise. For instance, if you want to improve the performance of spurious frequencies, you need to lower gate delays, have better matching between the up and down currents, and have a lesser loop bandwidth.

Video Highlights

00:24 - Introduction and recap of previous lesson
04:27 - Impact of increasing the capacitance on the tones and loop band width
13:30 - Trade-offs in designing a frequency synthesizer, including phase noise, settling time, and spurious frequencies
23:22 - Divide a frequency by a non-integer using a specific algorithm
41:39 - Phase detector output and the appearance of spurious frequencies

Key Takeaways

- The loop bandwidth is limited to a fraction of the reference frequency.
- Glitches on the control voltage can be reduced by increasing the capacitance, which in turn decreases the loop bandwidth.
- Dividing a frequency by non-integers can potentially improve phase noise performance and settling times.
- The output of the synthesizer mimics the reference within the loop bandwidth.
- The division by non-integers can be achieved by dividing certain cycles by a specific number and other cycles by another number.