Ansys HFSS 3D Layout for PCB

The Ansys HFSS 3D Layout course for high-speed printed circuit board design focuses on layered structures using the 3D Layout design type in HFSS and AEDT (Ansys Electronic Desktop). This course is designed for intermediate-advanced users and includes 5 modules. It covers Padstacks, IBIS and Eye source setups, Parametric study, Package-PCB-Connector layout driven assembly (LDA), and DC IR analysis. Workshops include differential via structures, sub-design cutouts from larger printed circuit boards, and full ECAD and MCAD structures and simulations that follow realistic workflows from start to finish.

Learning Outcomes:

Following completion of this workshop, you will be able to:

• • Work with Ansys HFSS 3D Layout via Padstack automation, Padstack definitions and usage.
  • Create differential vias, traces, and ground plane on different layers and assigning net names, boundary conditions and excitations.
  • Incorporate package, PCB and IBIS models in one environment and use the Nexxim transient circuit simulator from the layout interface of the AEDT.
  • Set up eye sources and terminations on the layout and generate eye diagrams.
  • Run parametric study to predict the performance of a PCB with manufacturing tolerance.
  • Combine MCAD and ECAD models and make sub-design cutouts at the desired extent in Ansys HFSS 3D Layout and analyze them all together.
  • Set up connector/package/board models in one environment and choose the solver. technology that is best for each simulation and run an LNA simulation on the concatenated model.
  • Set up a DC IR simulation and compute DC current and voltage distribution, plot DC IR field overlays, and export DC IR simulation results using Ansys HFSS 3D Layout.

Prerequisites:

• • Prior knowledge of Ansys HFSS 3D Layout Getting Started course is required.
  • Knowledge of high-speed digital circuit design, including S-parameters, transmission lines, and differential parts is highly recommended.
  • Knowledge of printed circuit board design, including vias, component reference designators, and layer stackups is valuable.