TAGGED: interconnect, simulation
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February 18, 2021 at 1:43 pm
leej
SubscriberHi,
I'm running into issues with different results from the output signal "sample" and "block" mode simulations. I took the standard "qpsk_qam_transceiver.icp" example, subtracted the PDs, and looked at the constellation diagrams.
In the attached picture, you can see the differences, which are quite significant. I am seeing that if I increase the "samples per bit" in sample mode, the results start to be more alike, but still not exactly the same. The "samples per bit" setting in block mode don't really matter for the results. I prefer to use block-based simulation mode and lower number of samples per bit for the speed of the simulations, but am sceptical of the results obtained. Can you explain in more details what exactly is causing the differences and how can I improve the block mode simulation to make it more realistic?
Thanks!
February 18, 2021 at 8:48 pmKyle
Ansys EmployeenI think Block mode should work well for a unidirectional circuit like this. I'm not sure exactly what is causing the differences between these results, however. It's a bit difficult to compare the constellation diagrams, can you please share the oscilloscope results? I think these results would give a better idea of what's going on in the circuit.nFebruary 19, 2021 at 11:10 amFebruary 19, 2021 at 11:12 amFebruary 22, 2021 at 8:55 pmKyle
Ansys EmployeeHello Array,nIt looks like the block and sample oscilloscope results are fairly similar, so the issue is likely with how the VSA and eye diagram analyzers are processing the data. In particular it looks like the timing is off for the sample mode results. It might help to add the outputs of the symbol mapper as reference signals to the VSA and eye diagram analyzers. This will allow for automatic delay compensation of the input signal. You can enable the reference signal input for the analyzers by setting their signal reference input property to true. Please try that and let me know if it helps. nViewing 4 reply threads- The topic ‘Simulation Result Differences Between Sample and Block Mode’ is closed to new replies.
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