Reply To: IR2110 gate driver model in ansys simplorer 2022.R1

[pradhan.5]

Hi MirandaH,

I could see Vhi_to_vs is about 13.2V as u mentioned. My question is why it is not a pulsating signal like Vg_Lo rather it is a flat line? Spice simulation shows both high side and low side output as pulsating signals with respect to what frequency we have set up.

 

Thanks 

SP