Reply To: Zo when applying bulk conductivity to the silicon substrate of finite-ground CPW

[DMARATHE]

Hi,

Thanks for posting your query on forum.

I am not very sure with limited information why the characteristic impedance graph is coming like that.

However, I have few suggestions. It is seen that S-parameters and port impedaces changes with wave port size. The right size of wave port and placement is recommened to avoid getting excited parallel plane waveguide mode.

Some recommenedtions :

Port width should be no less than 3 x the overall CPW width, or 3 x (2 g + w)  

Port height should be no less than 4 x the dielectric height, or 4 h

The wave port outline must contact the side grounds and should not exceeing lambad/2 in any direction

g = spacing between signal and ground trace, w = width of signal trace and h = substrate height

Thanks,