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April 1, 2025 at 2:44 pm
shupengli2024
SubscriberHi, I am using 2025R1 version, circuit mode to do a Nexxim transient simulation. I encountered an error: serializer::iff_writer(error): File layout grew beyond 4GiB limit. The working frequency is large ~MHz, but I need to do a long-time simulation ~100s. I guess the problem is the output data is too frequent. Is there anyway to reduce the outputting frenquency? I tried increasing the step time ~ 3 orders of magnitude in the analysis control, but the same error still exists. I am sure my disk is large enough with a NTFS format.
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April 2, 2025 at 4:32 am
Takeshi Itadani
Ansys EmployeeWhen analyzing in Circuit, analysis results are written to .sdf files, but the maximum file size is limited to 4 GB due to system limitations.
As a countermeasure, please review the analysis time, analysis steps, etc., and set the analysis settings so that the file size does not exceed 4 GB. -
April 2, 2025 at 2:26 pm
shupengli2024
SubscriberIs there anyway to bypass the 4GB limitation? or how can I reduce the output frequency to make my file smaller than 4GB?
For my case, I must simulate up to 100s with a 1MHz sinoidal input. I tried to use different analysis steps (10ns-100us), but the total time can only go up to 0.6s no matter the step length.
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April 2, 2025 at 4:53 pm
Gia
Ansys EmployeeCan you please explain more about why you need to simulate up to 100s with a 1MHz sinusoidal input? - Can you please post an image of your model/schematic?
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April 2, 2025 at 9:15 pm
shupengli2024
SubscriberSure, I used a rectifying circuit to study the charging time of a capacitor with AC input. Is there a more proper module to simulate it?
Otherwise, I am still wondering how to reduce the output frequency to make my file smaller than 4GB? Thanks in advance!
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