Noise Other Possible Topologies — Lesson 3

This lesson covers the design and evaluation of low noise amplifier (LNA) topologies in CMOS RF integrated circuits. It delves into the noise performance of a specific amplifier and explores other possible LNA topologies. The lesson explains the concept of source degeneration through an inductor, the conversion of current into voltage through a cascade mosfet, and the role of an inductive load for matching purposes. It also discusses the importance of biasing, the use of a current mirror, and the impact of parasitic capacitances. The lesson concludes with an exploration of noise cancellation techniques and the impact of gate resistance on noise generation.

Video Highlights

08:58 - Detailed analysis of the channel noise of the mosfet and the impact of parasitic capacitances
20:30 - Matching network, frequency and voltage
36:35 - Other topologies for LNA
42:18 - Discussion on the use of bipolar junction devices and mosfets in low noise amplifiers
48:24 - Noise cancellation techniques in low noise amplifiers

Key Takeaways

- The design of low noise amplifier (LNA) topologies in CMOS RF integrated circuits involves understanding the noise performance of the amplifier and exploring other possible LNA topologies.
- Source degeneration through an inductor and the conversion of current into voltage through a cascade mosfet are crucial aspects of the design.
- An inductive load is used for matching purposes, and biasing plays a significant role in the overall performance of the circuit.
- The use of a current mirror and the impact of parasitic capacitances are also important considerations.
- Noise cancellation techniques can be used to mitigate the impact of noise, and the gate resistance of a mosfet can significantly impact noise generation.