{"id":159040,"date":"2022-07-04T07:00:00","date_gmt":"2022-07-04T07:00:00","guid":{"rendered":"\/knowledge\/forums\/topic\/ansys-electronics-desktop-simple-communications-channel-for-signal-integrity-analyses-part-iii\/"},"modified":"2022-07-04T07:44:55","modified_gmt":"2022-07-04T07:44:55","slug":"ansys-electronics-desktop-simple-communications-channel-for-signal-integrity-analyses-part-iii","status":"publish","type":"topic","link":"https:\/\/innovationspace.ansys.com\/knowledge\/forums\/topic\/ansys-electronics-desktop-simple-communications-channel-for-signal-integrity-analyses-part-iii\/","title":{"rendered":"ANSYS Electronics Desktop: Simple Communications Channel For Signal Integrity Analyses &#8211; Part III"},"content":{"rendered":"<p>This tutorial describes how to specify and run QuickEye and VerifEye analyses in order to perform signal integrity analyses. ANSYS Electronics Desktop integrates rigorous electromagnetic analysis with system and circuit simulation in a comprehensive, easy-to-use design platform.<br \/>\n<iframe loading=\"lazy\" title=\"ANSYS Electronics Desktop: Simple Communications Channel For Signal Integrity Analyses - Part III\" width=\"640\" height=\"360\" src=\"https:\/\/www.youtube.com\/embed\/7Rry7M4qx8k?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe><\/p>\n","protected":false},"template":"","class_list":["post-159040","topic","type-topic","status-publish","hentry","topic-tag-ansys-electronics-desktop","topic-tag-bathtub-curves","topic-tag-circuit-design","topic-tag-circuit-schematic","topic-tag-contour-plots","topic-tag-differential-pair","topic-tag-eye-diagrams","topic-tag-eye-source","topic-tag-platform-for-electromagnetic","topic-tag-signal-integrity-analyses"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_wp_page_template":["default"],"_bbp_last_active_time":["3\/6\/2022 20:20"],"_bbp_forum_id":["27819"],"_btv_view_count":["8334"],"_edit_lock":["1656920867:76714"],"_edit_last":["76714"],"_bbp_topic_id":["159040"],"_oembed_5cce0eeacd9f2102f89bf4096d10a1c7":["<iframe title=\"ANSYS Electronics Desktop: Simple Communications Channel For Signal Integrity Analyses - Part III\" width=\"640\" height=\"360\" src=\"https:\/\/www.youtube.com\/embed\/7Rry7M4qx8k?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture\" allowfullscreen><\/iframe>"],"_oembed_time_5cce0eeacd9f2102f89bf4096d10a1c7":["1656920842"],"_oembed_777be0b693ac6fe2d0040648b81f6c67":["<iframe title=\"ANSYS Electronics Desktop: Simple Communications Channel For Signal Integrity Analyses - Part III\" width=\"640\" height=\"360\" src=\"https:\/\/www.youtube.com\/embed\/7Rry7M4qx8k?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>"],"_oembed_time_777be0b693ac6fe2d0040648b81f6c67":["1712193903"]},"test":"watchlearnansys-com"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/knowledge\/wp-json\/wp\/v2\/topics\/159040","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/knowledge\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/knowledge\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/knowledge\/wp-json\/wp\/v2\/topics\/159040\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/knowledge\/wp-json\/wp\/v2\/media?parent=159040"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}