{"id":54765,"date":"2021-04-27T15:42:36","date_gmt":"2021-04-27T15:42:36","guid":{"rendered":"\/forum\/forums\/topic\/odb-to-siwave-and-further-to-q3d-analysis-approach\/"},"modified":"2022-08-02T09:27:12","modified_gmt":"2022-08-02T09:27:12","slug":"odb-to-siwave-and-further-to-q3d-analysis-approach","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/odb-to-siwave-and-further-to-q3d-analysis-approach\/","title":{"rendered":"ODB++ to SiWave and further to Q3D analysis Approach"},"content":{"rendered":"

Hi,<\/p>\n

    \n
  1. What is the right approach for analyzing i.e. evaluating parasitics of\u00a0the pcb design with Altium? I am using ODB++ files of Altium, importing in SiWave and then exporting using Q3D extractor?<\/li>\n
  2. How do I ensure that the exported design for Q3D analysis has hollow vias? Under export options, this setting is unchecked “100% via fill (overrides per-padstack plating ratio)”. Just to give more context, I can only choose top and bottom faces of the vias within Electromangnetic suite while assigning excitation. If hollow vias are available, then I might be able to choose the inner cylinder of the via. How can I validate whether a hollow or filled via is exported using Q3D extractor option?<\/li>\n<\/ol>\n

    I will appreciate all your thoughts.<\/p>\n","protected":false},"template":"","class_list":["post-54765","topic","type-topic","status-closed","hentry","topic-tag-altium","topic-tag-q3d","topic-tag-siwave","topic-tag-via"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_old_topic_id":["27101"],"_bbp_old_topic_author_name_id":["Anonymous"],"_bbp_old_is_topic_anonymous_id":["false"],"_bbp_old_closed_status_id":["publish"],"_bbp_author_ip":["??2w"],"_bbp_old_sticky_status_id":["normal"],"_bbp_likes_count":["1"],"_btv_view_count":["2059"],"_bbp_subscription":["234472"],"_edit_lock":["1659455623:76739"],"_edit_last":["76739"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["54765"],"_bbp_forum_id":["27793"],"_bbp_engagement":["122","28551","184990","189966"],"_bbp_voice_count":["4"],"_bbp_reply_count":["8"],"_bbp_last_reply_id":["222997"],"_bbp_last_active_id":["222997"],"_bbp_last_active_time":["2021-05-05 15:15:36"]},"test":"bsr"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/54765","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/54765\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=54765"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}