{"id":428612,"date":"2025-04-11T03:05:05","date_gmt":"2025-04-11T03:05:05","guid":{"rendered":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/element-appears-to-be-connected-between-pin-groups-containing-no-valid-pins\/"},"modified":"2025-04-11T03:05:05","modified_gmt":"2025-04-11T03:05:05","slug":"element-appears-to-be-connected-between-pin-groups-containing-no-valid-pins","status":"publish","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/element-appears-to-be-connected-between-pin-groups-containing-no-valid-pins\/","title":{"rendered":"element appears to be connected between pin groups containing no valid pins"},"content":{"rendered":"<p>I want to add a resistor parallel to the capacitor on the board.&nbsp; However it reports error shown below when running PI simulation.<br \/>\n<img decoding=\"async\" src=\"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2025\/04\/11-04-2025-1744340348-mceclip0.png\" \/><br \/>\nI check the routing and find no problem.&nbsp;<br \/>\n<img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2025\/04\/11-04-2025-1744340589-mceclip2.png\" width=\"589\" height=\"300\" \/><br \/>\n<img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2025\/04\/11-04-2025-1744340636-mceclip3.png\" width=\"766\" height=\"91\" \/><\/p>\n","protected":false},"template":"","class_list":["post-428612","topic","type-topic","status-publish","hentry"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_forum_id":["27793"],"_bbp_topic_id":["428612"],"_bbp_subscription":["531329","2326"],"_bbp_author_ip":["203.85.68.211"],"_bbp_last_reply_id":["428932"],"_bbp_last_active_id":["428932"],"_bbp_last_active_time":["2025-04-15 00:38:53"],"_bbp_reply_count":["1"],"_bbp_reply_count_hidden":["0"],"_bbp_voice_count":["2"],"_bbp_engagement":["531329","2326"],"_btv_view_count":["150"],"_bbp_topic_status":["unanswered"],"_edit_lock":["1744354640:200"]},"test":"wan-wangnio-com"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/428612","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/428612\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=428612"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}