{"id":392471,"date":"2024-11-02T13:21:18","date_gmt":"2024-11-02T13:21:18","guid":{"rendered":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/how-to-define-one-input-two-output-rlgc-model-for-circuit-transient-simulation\/"},"modified":"2024-11-02T13:21:18","modified_gmt":"2024-11-02T13:21:18","slug":"how-to-define-one-input-two-output-rlgc-model-for-circuit-transient-simulation","status":"publish","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/how-to-define-one-input-two-output-rlgc-model-for-circuit-transient-simulation\/","title":{"rendered":"How to define one-input two-output RLGC model for circuit transient simulation"},"content":{"rendered":"

<p>I want to design a interconnect structure in semiconductor metal layer and know the new structure RLGC behaviour in circuit response. Interconnect structure generally have a source come from transistor output and multiple sink terminal for outside electrical connect. Unfortunately, I found that in Q3D extractor, I can’t  define one source and two sink, which can not meet my simulation requirment. If I define two source and one sink, and then connect the sink with transistor output and source with other outside electrical connect, I found that the spice model isn’t accurate. I would like to know if there are any methods that can define a one-input and two-output RLGC model for circuit simulation. Thank you very much.<\/p><\/p>\n","protected":false},"template":"","class_list":["post-392471","topic","type-topic","status-publish","hentry","topic-tag-ansys-circuit","topic-tag-designsemiconductor-1","topic-tag-q3d-extractor"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t