{"id":379549,"date":"2024-08-21T03:26:52","date_gmt":"2024-08-21T03:26:52","guid":{"rendered":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/"},"modified":"2024-08-21T03:26:52","modified_gmt":"2024-08-21T03:26:52","slug":"lattice-pair-on-unequal-conditions","status":"publish","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/","title":{"rendered":"Lattice Pair on unequal conditions"},"content":{"rendered":"<p>Hi,<\/p>\n<p>Here is my scheme:<\/p>\n<p><img decoding=\"async\" src=\"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2024\/08\/21-08-2024-1724210578-8.JPG\" alt=\"\"><\/p>\n<p>I need to define the boundary conditions (lattice pairs) for the side walls. As you can see, the shape of the top layer is different, which has led to errors in the matching boundary conditions. I would like to know how I can address this issue.<\/p>\n<p>I based this simulation on a shape described in a specific article.<\/p>\n<p>&nbsp;<\/p>\n<p><img decoding=\"async\" src=\"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2024\/08\/21-08-2024-1724210708-9.JPG\" alt=\"\"><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"template":"","class_list":["post-379549","topic","type-topic","status-publish","hentry","topic-tag-ansys-electronics-desktop"],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 4.9.10 - aioseo.com -->\n\t<meta name=\"description\" content=\"Hi,Here is my scheme:I need to define the boundary conditions (lattice pairs) for the side walls. As you can see, the shape of the top layer is different, which has led to errors in the matching boundary conditions. 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I would like to know how I can address this issue.I based this simulation on a shape\" \/>\n\t\t<meta property=\"og:url\" content=\"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/\" \/>\n\t\t<meta property=\"og:image\" content=\"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2024\/08\/21-08-2024-1724210578-8.JPG\" \/>\n\t\t<meta property=\"og:image:secure_url\" content=\"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2024\/08\/21-08-2024-1724210578-8.JPG\" \/>\n\t\t<meta property=\"article:published_time\" content=\"2024-08-21T03:26:52+00:00\" \/>\n\t\t<meta property=\"article:modified_time\" content=\"2024-08-21T03:26:52+00:00\" \/>\n\t\t<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n\t\t<meta name=\"twitter:title\" content=\"Lattice Pair on unequal conditions | Ansys Learning Forum\" \/>\n\t\t<meta name=\"twitter:description\" content=\"Hi,Here is my scheme:I need to define the boundary conditions (lattice pairs) for the side walls. As you can see, the shape of the top layer is different, which has led to errors in the matching boundary conditions. I would like to know how I can address this issue.I based this simulation on a shape\" \/>\n\t\t<meta name=\"twitter:image\" content=\"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2024\/08\/21-08-2024-1724210578-8.JPG\" \/>\n\t\t<script type=\"application\/ld+json\" class=\"aioseo-schema\">\n\t\t\t{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/forums\\\/topic\\\/lattice-pair-on-unequal-conditions\\\/#breadcrumblist\",\"itemListElement\":[{\"@type\":\"ListItem\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum#listItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\",\"nextItem\":{\"@type\":\"ListItem\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/topics\\\/#listItem\",\"name\":\"Topics\"}},{\"@type\":\"ListItem\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/topics\\\/#listItem\",\"position\":2,\"name\":\"Topics\",\"item\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/topics\\\/\",\"nextItem\":{\"@type\":\"ListItem\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/forums\\\/topic-tag\\\/ansys-electronics-desktop\\\/#listItem\",\"name\":\"ansys-electronics-desktop\"},\"previousItem\":{\"@type\":\"ListItem\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum#listItem\",\"name\":\"Home\"}},{\"@type\":\"ListItem\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/forums\\\/topic-tag\\\/ansys-electronics-desktop\\\/#listItem\",\"position\":3,\"name\":\"ansys-electronics-desktop\",\"item\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/forums\\\/topic-tag\\\/ansys-electronics-desktop\\\/\",\"nextItem\":{\"@type\":\"ListItem\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/forums\\\/topic\\\/lattice-pair-on-unequal-conditions\\\/#listItem\",\"name\":\"Lattice Pair on unequal conditions\"},\"previousItem\":{\"@type\":\"ListItem\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/topics\\\/#listItem\",\"name\":\"Topics\"}},{\"@type\":\"ListItem\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/forums\\\/topic\\\/lattice-pair-on-unequal-conditions\\\/#listItem\",\"position\":4,\"name\":\"Lattice Pair on unequal conditions\",\"previousItem\":{\"@type\":\"ListItem\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/forums\\\/topic-tag\\\/ansys-electronics-desktop\\\/#listItem\",\"name\":\"ansys-electronics-desktop\"}}]},{\"@type\":\"Organization\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/#organization\",\"name\":\"Ansys Learning Forum\",\"description\":\"Ansys Innovation Space\",\"url\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/forums\\\/topic\\\/lattice-pair-on-unequal-conditions\\\/#webpage\",\"url\":\"https:\\\/\\\/innovationspace.ansys.com\\\/forum\\\/forums\\\/topic\\\/lattice-pair-on-unequal-conditions\\\/\",\"name\":\"Lattice Pair on unequal conditions | Ansys Learning Forum\",\"description\":\"Hi,Here is my scheme:I need to define the boundary conditions (lattice pairs) for the side walls. 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As you can see, the shape of the top layer is different, which has led to errors in the matching boundary conditions. I would like to know how I can address this issue.I based this simulation on a shape","canonical_url":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/","robots":"max-image-preview:large","keywords":"","webmasterTools":{"miscellaneous":""},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"BreadcrumbList","@id":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/#breadcrumblist","itemListElement":[{"@type":"ListItem","@id":"https:\/\/innovationspace.ansys.com\/forum#listItem","position":1,"name":"Home","item":"https:\/\/innovationspace.ansys.com\/forum","nextItem":{"@type":"ListItem","@id":"https:\/\/innovationspace.ansys.com\/forum\/topics\/#listItem","name":"Topics"}},{"@type":"ListItem","@id":"https:\/\/innovationspace.ansys.com\/forum\/topics\/#listItem","position":2,"name":"Topics","item":"https:\/\/innovationspace.ansys.com\/forum\/topics\/","nextItem":{"@type":"ListItem","@id":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic-tag\/ansys-electronics-desktop\/#listItem","name":"ansys-electronics-desktop"},"previousItem":{"@type":"ListItem","@id":"https:\/\/innovationspace.ansys.com\/forum#listItem","name":"Home"}},{"@type":"ListItem","@id":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic-tag\/ansys-electronics-desktop\/#listItem","position":3,"name":"ansys-electronics-desktop","item":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic-tag\/ansys-electronics-desktop\/","nextItem":{"@type":"ListItem","@id":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/#listItem","name":"Lattice Pair on unequal conditions"},"previousItem":{"@type":"ListItem","@id":"https:\/\/innovationspace.ansys.com\/forum\/topics\/#listItem","name":"Topics"}},{"@type":"ListItem","@id":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/#listItem","position":4,"name":"Lattice Pair on unequal conditions","previousItem":{"@type":"ListItem","@id":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic-tag\/ansys-electronics-desktop\/#listItem","name":"ansys-electronics-desktop"}}]},{"@type":"Organization","@id":"https:\/\/innovationspace.ansys.com\/forum\/#organization","name":"Ansys Learning Forum","description":"Ansys Innovation Space","url":"https:\/\/innovationspace.ansys.com\/forum\/"},{"@type":"WebPage","@id":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/#webpage","url":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/","name":"Lattice Pair on unequal conditions | Ansys Learning Forum","description":"Hi,Here is my scheme:I need to define the boundary conditions (lattice pairs) for the side walls. As you can see, the shape of the top layer is different, which has led to errors in the matching boundary conditions. I would like to know how I can address this issue.I based this simulation on a shape","inLanguage":"en-US","isPartOf":{"@id":"https:\/\/innovationspace.ansys.com\/forum\/#website"},"breadcrumb":{"@id":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/#breadcrumblist"},"datePublished":"2024-08-21T03:26:52+00:00","dateModified":"2024-08-21T03:26:52+00:00"},{"@type":"WebSite","@id":"https:\/\/innovationspace.ansys.com\/forum\/#website","url":"https:\/\/innovationspace.ansys.com\/forum\/","name":"Ansys Learning Forum","description":"Ansys Innovation Space","inLanguage":"en-US","publisher":{"@id":"https:\/\/innovationspace.ansys.com\/forum\/#organization"}}]},"og:locale":"en_US","og:site_name":"Ansys Learning Forum | Ansys Innovation Space","og:type":"article","og:title":"Lattice Pair on unequal conditions | Ansys Learning Forum","og:description":"Hi,Here is my scheme:I need to define the boundary conditions (lattice pairs) for the side walls. As you can see, the shape of the top layer is different, which has led to errors in the matching boundary conditions. I would like to know how I can address this issue.I based this simulation on a shape","og:url":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/","og:image":"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2024\/08\/21-08-2024-1724210578-8.JPG","og:image:secure_url":"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2024\/08\/21-08-2024-1724210578-8.JPG","article:published_time":"2024-08-21T03:26:52+00:00","article:modified_time":"2024-08-21T03:26:52+00:00","twitter:card":"summary_large_image","twitter:title":"Lattice Pair on unequal conditions | Ansys Learning Forum","twitter:description":"Hi,Here is my scheme:I need to define the boundary conditions (lattice pairs) for the side walls. As you can see, the shape of the top layer is different, which has led to errors in the matching boundary conditions. I would like to know how I can address this issue.I based this simulation on a shape","twitter:image":"https:\/\/innovationspace.ansys.com\/forum\/wp-content\/uploads\/sites\/2\/2024\/08\/21-08-2024-1724210578-8.JPG"},"aioseo_meta_data":{"post_id":"379549","title":null,"description":null,"keywords":null,"keyphrases":null,"primary_term":null,"canonical_url":null,"og_title":null,"og_description":null,"og_object_type":"default","og_image_type":"content","og_image_url":null,"og_image_width":null,"og_image_height":null,"og_image_custom_url":null,"og_image_custom_fields":null,"og_video":null,"og_custom_url":null,"og_article_section":null,"og_article_tags":null,"twitter_use_og":true,"twitter_card":"default","twitter_image_type":"default","twitter_image_url":null,"twitter_image_custom_url":null,"twitter_image_custom_fields":null,"twitter_title":null,"twitter_description":null,"schema":{"blockGraphs":[],"customGraphs":[],"default":{"data":{"Article":[],"Course":[],"Dataset":[],"FAQPage":[],"Movie":[],"Person":[],"Product":[],"ProductReview":[],"Car":[],"Recipe":[],"Service":[],"SoftwareApplication":[],"WebPage":[]},"graphName":"","isEnabled":true},"graphs":[]},"schema_type":"default","schema_type_options":null,"pillar_content":false,"robots_default":true,"robots_noindex":false,"robots_noarchive":false,"robots_nosnippet":false,"robots_nofollow":false,"robots_noimageindex":false,"robots_noodp":false,"robots_notranslate":false,"robots_max_snippet":null,"robots_max_videopreview":null,"robots_max_imagepreview":"large","priority":null,"frequency":null,"local_seo":null,"limit_modified_date":false,"created":"2024-10-28 16:32:15","updated":"2024-10-28 16:32:15","ai":null,"breadcrumb_settings":null,"seo_analyzer_scan_date":null},"aioseo_breadcrumb":"<div class=\"aioseo-breadcrumbs\"><span class=\"aioseo-breadcrumb\">\n\t\t\t<a href=\"https:\/\/innovationspace.ansys.com\/forum\" title=\"Home\">Home<\/a>\n\t\t<\/span><span class=\"aioseo-breadcrumb-separator\">&raquo;<\/span><span class=\"aioseo-breadcrumb\">\n\t\t\t<a href=\"https:\/\/innovationspace.ansys.com\/forum\/topics\/\" title=\"Topics\">Topics<\/a>\n\t\t<\/span><span class=\"aioseo-breadcrumb-separator\">&raquo;<\/span><span class=\"aioseo-breadcrumb\">\n\t\t\t<a href=\"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic-tag\/ansys-electronics-desktop\/\" title=\"ansys-electronics-desktop\">ansys-electronics-desktop<\/a>\n\t\t<\/span><span class=\"aioseo-breadcrumb-separator\">&raquo;<\/span><span class=\"aioseo-breadcrumb\">\n\t\t\tLattice Pair on unequal conditions\n\t\t<\/span><\/div>","aioseo_breadcrumb_json":[{"label":"Home","link":"https:\/\/innovationspace.ansys.com\/forum"},{"label":"Topics","link":"https:\/\/innovationspace.ansys.com\/forum\/topics\/"},{"label":"ansys-electronics-desktop","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic-tag\/ansys-electronics-desktop\/"},{"label":"Lattice Pair on unequal conditions","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/lattice-pair-on-unequal-conditions\/"}],"acf":[],"custom_fields":[{"0":{"_bbp_subscription":["349241","49994"],"_bbp_author_ip":["45.77.216.94"]," _bbp_last_reply_id":["0"]," _bbp_likes_count":["0"],"_btv_view_count":["225"],"_bbp_topic_status":["unanswered"],"_bbp_topic_id":["379549"],"_bbp_forum_id":["27793"],"_bbp_engagement":["49994","349241"],"_bbp_voice_count":["2"],"_bbp_reply_count":["2"],"_bbp_last_reply_id":["381349"],"_bbp_last_active_id":["381349"],"_bbp_last_active_time":["2024-09-02 14:22:03"]},"test":"vphaseasu-edu"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/379549","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/379549\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=379549"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}