{"id":367405,"date":"2024-05-17T19:34:24","date_gmt":"2024-05-17T19:34:24","guid":{"rendered":"\/forum\/forums\/topic\/ansys-ddr4-compliance-toolkit\/"},"modified":"2024-05-17T19:35:07","modified_gmt":"2024-05-17T19:35:07","slug":"ansys-ddr4-compliance-toolkit","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/ansys-ddr4-compliance-toolkit\/","title":{"rendered":"Ansys DDR4 Compliance Toolkit"},"content":{"rendered":"<p>Hi, I am new to Ansys DDR4 simulation. I followed the DDR wizard in SIwave and automatically created schematic in desktop. But when I generate compliance report, I am keep getting eyediagram where DQ and DQs intersects with each other. It seems a paramter issue (phase shift or delay for DQs?) but i don&#8217;t know how to adjust it. Could you help me with this. Thanks!<\/p>\n<p><img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2024\/05\/17-05-2024-1715974233-Screenshot 2024-05-17 152953.png\" alt=\"\"><\/p>\n","protected":false},"template":"","class_list":["post-367405","topic","type-topic","status-closed","hentry","topic-tag-ansys-electronics-desktop","topic-tag-AnsysSiwave-1","topic-tag-toolkit"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_subscription":["134723","452017"],"_bbp_author_ip":["184.24.96.177"]," _bbp_last_reply_id":["0"]," _bbp_likes_count":["0"],"_btv_view_count":["964"],"_bbp_topic_status":["answered"],"_bbp_topic_id":["367405"],"_bbp_forum_id":["27793"],"_bbp_engagement":["134723","452017"],"_bbp_voice_count":["2"],"_bbp_last_reply_id":["381675"],"_bbp_last_active_id":["381675"],"_bbp_last_active_time":["2024-09-05 19:45:15"]},"test":"cchenteradar-com"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/367405","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":1,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/367405\/revisions"}],"predecessor-version":[{"id":367406,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/367405\/revisions\/367406"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=367405"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}