


{"id":31402,"date":"2018-11-08T14:32:58","date_gmt":"2018-11-08T14:32:58","guid":{"rendered":"\/forum\/forums\/topic\/issue-when-running-analysis-on-circuit-design-tool\/"},"modified":"2018-11-08T14:32:58","modified_gmt":"2018-11-08T14:32:58","slug":"issue-when-running-analysis-on-circuit-design-tool","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/issue-when-running-analysis-on-circuit-design-tool\/","title":{"rendered":"Issue when running analysis on circuit design tool"},"content":{"rendered":"<p>Hi,<\/p>\n<p><\/p>\n<p>I&#8217;m having trouble running analysis on the ciruit design tool on Ansys. From HFSS, I export s-parameters as an .sNp file, and then I open it up on the ciruit design tool. My first concern is I&#8217;m importing a 2 port network, but I&#8217;m not sure why 4 terminals aren&#8217;t begin shown; instead the ports are represented by a box on either side.<\/p>\n<p><\/p>\n<p><img decoding=\"async\" src=\"https:\/\/us.v-cdn.net\/6032193\/uploads\/attachments\/776e1892-0efa-46ce-bde8-a9820152113b\/c7e77dea-f4c4-4515-a061-a99200e6ebad_capture-5.jpg?width=690&amp;upscale=false\" alt=\"\"><\/p>\n<p><\/p>\n<p>After importing the s parameters for the two port network and putting it inside my circuit, I realized the program wasn&#8217;t recognizing the ports. After some research, I learned that perhaps importing the s-parameters aren&#8217;t enough and&nbsp; I need to add the port symbol on each end of the port box, seen below. The simulation ran and I was able to get a plot for s-parameters. Do<span style=\"display: inline !important; float: none; background-color: transparent; color: #3b3b3b; font-family: Arial,Helvetica,sans-serif; font-size: 14px; font-style: normal; font-variant: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-decoration: none; text-indent: 0px; text-transform: none; -webkit-text-stroke-width: 0px; white-space: normal; word-spacing: 0px;\"> you think including the port component (diamond symbol) connected to the port boxes (what I got when I initially imported the s-param data) is the correct thing to do? I ask because I&#8217;ve also gotten this warning after analysis was done:&nbsp;<\/span><br style=\"background-color: transparent; color: #3b3b3b; font-family: Arial,Helvetica,sans-serif; font-size: 14px; font-style: normal; font-variant: normal; font-weight: 400; letter-spacing: normal; min-height: 0px; orphans: 2; text-align: left; text-decoration: none; text-indent: 0px; text-transform: none; -webkit-text-stroke-width: 0px; white-space: normal; word-spacing: 0px;\"><span style=\"display: inline !important; float: none; background-color: transparent; color: #3b3b3b; font-family: Arial,Helvetica,sans-serif; font-size: 14px; font-style: normal; font-variant: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-decoration: none; text-indent: 0px; text-transform: none; -webkit-text-stroke-width: 0px; white-space: normal; word-spacing: 0px;\">&nbsp;&#8221; [warning] Direct connections between interface and\/or global ports are not allowed: Pin, 0 and Net, Port2 &#8221;&nbsp;<\/span><\/p>\n<p><\/p>\n<p><img decoding=\"async\" src=\"https:\/\/us.v-cdn.net\/6032193\/uploads\/attachments\/776e1892-0efa-46ce-bde8-a9820152113b\/3c2fbbf8-8d1c-4d89-8bb9-a99200e75c28_capture-6.jpg?width=690&amp;upscale=false\" alt=\"\"><\/p>\n<p><\/p>\n<p>Next, I needed to integrate the ports back into my circuit but the simulation doesn&#8217;t work now. It says &#8221; Nothing to solve for LinearFrequency. Enable or clean up solution to force a new simulation.&#8221; &nbsp; Below is my circuit; any suggestions about what I&#8217;m doing wrong would be appreciated.&nbsp; I&#8217;m trying to do the same thing I did above, which is sweep for frequency and plot s-parameters. I got plots with above ciruit design without connecting any components additional components, but now for the ciruit below it isn&#8217;t working.<\/p>\n<p><\/p>\n<p>Do you think it&#8217;s anything related to a license issue (I have the gui for the ciruit tool, but no solve license; however if the license was the issue, I&#8217;m assuming the first circuit design above wouldn&#8217;t even run)?<\/p>\n<p><\/p>\n<p><img decoding=\"async\" src=\"https:\/\/us.v-cdn.net\/6032193\/uploads\/attachments\/776e1892-0efa-46ce-bde8-a9820152113b\/77c5a951-960f-42a8-8971-a99200ea1fe6_capture-7.jpg?width=690&amp;upscale=false\" alt=\"\"><\/p>\n<p><\/p>\n<p>&nbsp;<\/p>\n<p><\/p>\n<p><span style=\"display: inline !important; float: none; background-color: transparent; color: #3b3b3b; font-family: Arial,Helvetica,sans-serif; font-size: 14px; font-style: normal; font-variant: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-decoration: none; text-indent: 0px; text-transform: none; -webkit-text-stroke-width: 0px; white-space: normal; word-spacing: 0px;\">Also, do you know how to get the 4 terminals (2 terminals on either side) for the 2 port network (like below) because I end up connecting the capacitor back to the same node. Does the port box represent the 2 nodes?&nbsp;<\/span><\/p>\n<p><\/p>\n<p>&nbsp;<\/p>\n<p><\/p>\n<p><img decoding=\"async\" src=\"https:\/\/us.v-cdn.net\/6032193\/uploads\/attachments\/776e1892-0efa-46ce-bde8-a9820152113b\/a88e8990-8489-4056-a141-a99200eb9532_capture8.jpg?width=690&amp;upscale=false\" alt=\"\"><\/p>\n<p><\/p>\n<p>&nbsp;&nbsp;<\/p>\n","protected":false},"template":"","class_list":["post-31402","topic","type-topic","status-closed","hentry"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_old_topic_id":["3574"],"_bbp_old_topic_author_name_id":["Anonymous"],"_bbp_old_is_topic_anonymous_id":["false"],"_bbp_old_closed_status_id":["publish"],"_bbp_author_ip":[null],"_bbp_old_sticky_status_id":["normal"],"_bbp_likes_count":["1","1","1","1","1"],"_btv_view_count":["1910"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["31402"],"_bbp_forum_id":["27793"],"_bbp_engagement":["159799"],"_bbp_voice_count":["1"],"_bbp_reply_count":["2"],"_bbp_last_reply_id":["68862"],"_bbp_last_active_id":["68862"],"_bbp_last_active_time":["2018-11-08 17:01:34"]},"test":"hgar96"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/31402","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/31402\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=31402"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}