


{"id":309565,"date":"2023-10-01T02:45:01","date_gmt":"2023-10-01T02:45:01","guid":{"rendered":"\/forum\/forums\/topic\/ansys-unable-to-mesh-an-object-without-giving-me-any-error\/"},"modified":"2023-10-12T15:39:19","modified_gmt":"2023-10-12T15:39:19","slug":"ansys-unable-to-mesh-an-object-without-giving-me-any-error","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/ansys-unable-to-mesh-an-object-without-giving-me-any-error\/","title":{"rendered":"Ansys unable to mesh an object without giving me any error."},"content":{"rendered":"<p>My model consists of a small rectangle of size (0.5 um x 30 nm) shunting the capacitors of interdigital capacitors (IDC). I was able to mesh a larger nanowire of size (5 um x 100 nm) by assigning mesh operatrions of maximum element size of 500 nm and aspect ratio of 3.<\/p>\n<p>However, for the current design, HFSS would not even give me an error message while not meshing the rectangle at all. The only error message I got was &#8220;Plot Mesh1 becomes invalid due to no available mesh&#8221;.<\/p>\n<p>Attached is the screen shot of the two rectangles shunting IDC. As you can see, HFSS correctly meshes larger rectangle of width 50 nm, but it fails to mesh smaller rectangle of width 25 nm.<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/10\/01-10-2023-1696128263-mceclip0.png\" width=\"1027\" height=\"566\"><\/p>\n","protected":false},"template":"","class_list":["post-309565","topic","type-topic","status-closed","hentry","topic-tag-adaptivemesh-2","topic-tag-AnsysMaxwellelectronics-1","topic-tag-mesh"],"aioseo_notices":[],"aioseo_head":"\n\t\t<!-- All in One SEO 4.9.10 - aioseo.com -->\n\t<meta name=\"description\" content=\"My model consists of a small rectangle of size (0.5 um x 30 nm) shunting the capacitors of interdigital capacitors (IDC). I was able to mesh a larger nanowire of size (5 um x 100 nm) by assigning mesh operatrions of maximum element size of 500 nm and aspect ratio of 3.However, for the current\" \/>\n\t<meta name=\"robots\" content=\"max-image-preview:large\" \/>\n\t<link rel=\"canonical\" href=\"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/ansys-unable-to-mesh-an-object-without-giving-me-any-error\/\" \/>\n\t<meta name=\"generator\" content=\"All in One SEO (AIOSEO) 4.9.10\" \/>\n\t\t<meta property=\"og:locale\" content=\"en_US\" \/>\n\t\t<meta property=\"og:site_name\" content=\"Ansys Learning Forum | Ansys Innovation Space\" \/>\n\t\t<meta property=\"og:type\" content=\"article\" \/>\n\t\t<meta property=\"og:title\" content=\"Ansys unable to mesh an object without giving me any error. | Ansys Learning Forum\" \/>\n\t\t<meta property=\"og:description\" content=\"My model consists of a small rectangle of size (0.5 um x 30 nm) shunting the capacitors of interdigital capacitors (IDC). I was able to mesh a larger nanowire of size (5 um x 100 nm) by assigning mesh operatrions of maximum element size of 500 nm and aspect ratio of 3.However, for the current\" \/>\n\t\t<meta property=\"og:url\" content=\"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/ansys-unable-to-mesh-an-object-without-giving-me-any-error\/\" \/>\n\t\t<meta property=\"og:image\" content=\"https:\/\/innovationspace.ansys.com\/forum\/forum\/wp-content\/uploads\/sites\/2\/2023\/10\/01-10-2023-1696128263-mceclip0.png\" \/>\n\t\t<meta property=\"og:image:secure_url\" content=\"https:\/\/innovationspace.ansys.com\/forum\/forum\/wp-content\/uploads\/sites\/2\/2023\/10\/01-10-2023-1696128263-mceclip0.png\" \/>\n\t\t<meta property=\"article:published_time\" content=\"2023-10-01T02:45:01+00:00\" \/>\n\t\t<meta property=\"article:modified_time\" content=\"2023-10-12T15:39:19+00:00\" \/>\n\t\t<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n\t\t<meta name=\"twitter:title\" content=\"Ansys unable to mesh an object without giving me any error. | Ansys Learning Forum\" \/>\n\t\t<meta name=\"twitter:description\" content=\"My model consists of a small rectangle of size (0.5 um x 30 nm) shunting the capacitors of interdigital capacitors (IDC). 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