{"id":306275,"date":"2023-09-12T03:52:31","date_gmt":"2023-09-12T03:52:31","guid":{"rendered":"\/forum\/forums\/topic\/problem-with-interfacing-between-klayout-and-interconnect\/"},"modified":"2023-09-12T04:12:32","modified_gmt":"2023-09-12T04:12:32","slug":"problem-with-interfacing-between-klayout-and-interconnect","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/problem-with-interfacing-between-klayout-and-interconnect\/","title":{"rendered":"problem with interfacing between klayout and interconnect"},"content":{"rendered":"<p>Hi , I am simulating the RING MODULATOR&nbsp; in AMF Technology from one of the example &#8220;AMF_1_RingMod.gds&#8221;. (link for file:&nbsp;<\/p>\n<p><a title=\"AMF_1_RingMod.gds\" href=\"https:\/\/drive.google.com\/file\/d\/1KMvLglfiNC1Hr3k8Ui_NBLSx6pCRJvkl\/view?usp=sharing\">https:\/\/drive.google.com\/file\/d\/1KMvLglfiNC1Hr3k8Ui_NBLSx6pCRJvkl\/view?usp=sharing<\/a> &nbsp;<\/p>\n<p>Here , I am sharing design and error in interconnect window.&nbsp; Kindly help me to solve this issue. I have installed all the library in interconnect.<\/p>\n<ol>\n<li>design:<a class=\"wp-colorbox-image cboxElement\" href=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/09\/12-09-2023-1694490643-mceclip4.png\"><img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/09\/12-09-2023-1694490643-mceclip4.png\"><\/a>&nbsp;<\/li>\n<li><a class=\"wp-colorbox-image cboxElement\" href=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/09\/12-09-2023-1694490527-mceclip2.png\"><img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/09\/12-09-2023-1694490527-mceclip2.png\"><\/a><a class=\"wp-colorbox-image cboxElement\" href=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/09\/12-09-2023-1694490573-mceclip3.png\"><img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/09\/12-09-2023-1694490573-mceclip3.png\"><\/a><a class=\"wp-colorbox-image cboxElement\" href=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/09\/12-09-2023-1694489651-mceclip0.png\"><img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/09\/12-09-2023-1694489651-mceclip0.png\"><\/a><\/li>\n<\/ol>\n","protected":false},"template":"","class_list":["post-306275","topic","type-topic","status-closed","hentry","topic-tag-photonics"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_subscription":["23372","3002"],"_bbp_author_ip":["23.52.43.81"]," _bbp_last_reply_id":["0"]," _bbp_likes_count":["0"],"_btv_view_count":["242"],"_edit_lock":["1694491747:228949"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["306275"],"_bbp_forum_id":["27833"],"_bbp_engagement":["3002","23372"],"_bbp_voice_count":["2"],"_bbp_reply_count":["6"],"_bbp_last_reply_id":["310126"],"_bbp_last_active_id":["310126"],"_bbp_last_active_time":["2023-10-04 21:26:40"]},"test":"veerpalkauruvic-ca"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/306275","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/306275\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=306275"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}