{"id":301765,"date":"2023-08-16T21:00:41","date_gmt":"2023-08-16T21:00:41","guid":{"rendered":"\/forum\/forums\/topic\/klayout-interconnect-interoperability\/"},"modified":"2023-08-16T21:00:41","modified_gmt":"2023-08-16T21:00:41","slug":"klayout-interconnect-interoperability","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/klayout-interconnect-interoperability\/","title":{"rendered":"KLayout INTERCONNECT interoperability"},"content":{"rendered":"

I am struggling to properly interface between gdsfactory, klayout and interconnect.Currently, I am able to generate a layout in klayout based on gdsfactory scripts. I can also confirm that I can launch and run a circuit simulation in Interconnect from KLayout when following this tutorial:
https:\/\/optics.ansys.com\/hc\/en-us\/articles\/4411329984147-KLayout-INTERCONNECT-interoperability-Wavelength-Division-Multiplexing-WDM-<\/a><\/p>\n

In my circuit, I’d like to use gdsfactory and the siepic\/ubcpdk components. I expected that I should be able to define a circuit in gdsfactory, look over the layout in klayout, and then export it to Interconnect to run circuit simulations. However, that doesn’t seem to work. When I try that, Interconnect throws some errors such as “Error loading netlist: the element ‘straight_c2dabf47’ is not available in the library.” “Straight” is the name of the straight waveguide component, as described here:
https:\/\/gdsfactory.github.io\/ubc\/components_plot.html#straight<\/a><\/p>\n

I think the reason that this error doesn’t come up when following the tutorial is because it uses the Lumfoundry PDK. Each component in this PDK (waveguides, couplers etc) has a PCell and an associated Lumerical compact model.<\/p>\n

Alternatively, we’ve figured that hand-drawn paths in Klayout can be converted to working waveguide objects in Interconnect using the “SiEPIC > Waveguides > Path to Waveguides” menu item.<\/p>\n

But I haven’t been able to use any ordinary routing\/waveguide components in Interconnect. There just doesn’t seem to be a compact model for those components. How do we get these to work to complete the workflow?<\/p>\n","protected":false},"template":"","class_list":["post-301765","topic","type-topic","status-closed","hentry","topic-tag-interconnect","topic-tag-klayout"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t