{"id":292830,"date":"2023-07-12T17:58:10","date_gmt":"2023-07-12T17:58:10","guid":{"rendered":"\/forum\/forums\/topic\/ile-size-in-layout-mode-larger-than-memory-layout-size-in-analysis-mode\/"},"modified":"2023-07-12T18:02:01","modified_gmt":"2023-07-12T18:02:01","slug":"ile-size-in-layout-mode-larger-than-memory-layout-size-in-analysis-mode","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/ile-size-in-layout-mode-larger-than-memory-layout-size-in-analysis-mode\/","title":{"rendered":"File Size in Layout Mode larger than Memory Layout Size in Analysis Mode"},"content":{"rendered":"<p dir=\"auto\">The size of my .fsp simulation file in layout mode is larger than the expected file size of the simulation in analysis mode. The file size in layout mode should be around 500 &#8211; 600 Mb but for some reason, it is currently at 9.1 Gb. The memory report states that the monitor data saved to the .fsp file is only around 3.2 Gb after running the simulation.<\/p>\n<p dir=\"auto\">This has happened on numerous occasions for me with different files and I had to create a new file and copy and paste the FDTD layout to rerun the simulation without taking up too much memory to store and run the simulation. Is there something that I can do to somehow clear the cache and\/or reset the file size to its appropriate size?<\/p>\n<p dir=\"auto\"><img loading=\"lazy\" decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/07\/12-07-2023-1689184911-07122023_Lumerical FDTD Layout.png\" alt=\"\" width=\"285\" height=\"151\"><\/p>\n<p dir=\"auto\"><a class=\"wp-colorbox-image cboxElement\" href=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/07\/12-07-2023-1689184646-07122023_Lumerical FDTD Memory Report.png\"><img loading=\"lazy\" decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/07\/12-07-2023-1689184646-07122023_Lumerical FDTD Memory Report.png\" alt=\"\" width=\"282\" height=\"199\"><\/a><\/p>\n<p dir=\"auto\"><a class=\"wp-colorbox-image cboxElement\" href=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/07\/12-07-2023-1689184672-07122023_Lumerical FDTD File Size Layout Mode.png\"><img loading=\"lazy\" decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/07\/12-07-2023-1689184672-07122023_Lumerical FDTD File Size Layout Mode.png\" alt=\"\" width=\"462\" height=\"24\"><\/a><\/p>\n","protected":false},"template":"","class_list":["post-292830","topic","type-topic","status-closed","hentry"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_subscription":["289249","33648"],"_bbp_author_ip":["168.143.243.24"]," _bbp_last_reply_id":["0"]," _bbp_likes_count":["0"],"_btv_view_count":["905"],"_edit_lock":["1689184841:223925"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["292830"],"_bbp_forum_id":["27833"],"_bbp_engagement":["33648","289249"],"_bbp_voice_count":["2"],"_bbp_reply_count":["5"],"_bbp_last_reply_id":["293006"],"_bbp_last_active_id":["293006"],"_bbp_last_active_time":["2023-07-13 22:02:25"]},"test":"6c200ccdedecc3c93c24e650b45f1b0c19be2146"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/292830","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/292830\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=292830"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}