


{"id":280800,"date":"2023-04-23T06:56:53","date_gmt":"2023-04-23T06:56:53","guid":{"rendered":"\/forum\/forums\/topic\/run-verilog-a-pam4-transceiver-example-report-errors\/"},"modified":"2023-04-23T06:56:53","modified_gmt":"2023-04-23T06:56:53","slug":"run-verilog-a-pam4-transceiver-example-report-errors","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/run-verilog-a-pam4-transceiver-example-report-errors\/","title":{"rendered":"run Verilog-A PAM4 Transceiver example report errors"},"content":{"rendered":"<p>Dear Lumerical Support team,<\/p>\n<p>When I downloaded the&nbsp; example &lsquo;Verilog-A PAM4 Transceiver&rsquo; from <a href=\"https:\/\/optics.ansys.com\/hc\/en-us\/articles\/360042910313\">Verilog-A PAM4 Transceiver &#8211; Cadence Interoperability &ndash; Ansys Optics<\/a>,&nbsp; errors were reported after running it in Cadence Virtuoso, I followed the tutorial at the link step by step and did not make any changes, errors were as follows:<\/p>\n<p>&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;-<\/p>\n<p>ERROR (WIA-1175): Cannot plot waveform signals because no waveform data is available for plotting.<br \/>One of the possible reasons can be that &#8216;Save&#8217; check box for these signals are not selected in the Outputs Setup pane. Ensure that these check boxes are selected before you run the simulation.<br \/>ERROR (EXPLORER-5031): While simulating run ExplorerRun.0, point 1, test Sim:INV_VTH:1, received error:<br \/>Simulation Error:<br \/>&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;<br \/>Simulator failed to complete the simulation.<br \/>The simulator process returned a non-zero exit code, indicating failure.<br \/>The simulator could have crashed or intentionally returned to indicate an error.<br \/>Check the simulator log file for more information.&nbsp;&nbsp;Common causes:<br \/>1. Simulator may have crashed during exit even after reporting success in log file.<br \/>2. Abrupt automatic simulator termination (e.g., SIGKILL) because the simulator process has<br \/>&nbsp; &nbsp;exceeded resource limits, which can be specified in the distribution system or<br \/>&nbsp; &nbsp;by the kernel itself (e.g., the Linux OOMKiller).<br \/>3. Manual termination of the simulator process.<br \/>.\/runSimulation can be manually run in this directory to check the issue.<\/p>\n<p>&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;&#8212;<\/p>\n<p>Do you know any possible reasons for the errors reported\uff1f<\/p>\n<p>My software version\uff1a<\/p>\n<p>Cadence Virtuoso ICADVM18.1\uff1b<\/p>\n<p>Spectre191\uff1b<\/p>\n<p>&nbsp;<\/p>\n<p>The &#8216;save&#8217; check box mentioned in ERROR1175, the screenshot of the example in the above link is selected, but when I run it, it is grayed out and cannot be selected\uff1b<br \/>As for ERROR5031, I&#8217;m not sure what the reason is?<\/p>\n<p><img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/04\/23-04-2023-1682232780-cadence_interop_verilog-a_pam4_ade.PNG\" alt=\"\"><\/p>\n<p>thankyou\uff01<\/p>\n","protected":false},"template":"","class_list":["post-280800","topic","type-topic","status-closed","hentry"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_subscription":["283021","267175","14496"],"_bbp_author_ip":["23.220.96.180"]," _bbp_last_reply_id":["0"]," _bbp_likes_count":["0"],"_btv_view_count":["1622"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["280800"],"_bbp_forum_id":["27835"],"_bbp_engagement":["14496","267175","283021"],"_bbp_voice_count":["3"],"_bbp_reply_count":["4"],"_bbp_last_reply_id":["282825"],"_bbp_last_active_id":["282825"],"_bbp_last_active_time":["2023-05-08 13:06:46"]},"test":"1505503830qq-com"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/280800","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/280800\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=280800"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}