{"id":279621,"date":"2023-04-15T14:47:44","date_gmt":"2023-04-15T14:47:44","guid":{"rendered":"\/forum\/?post_type=topic&#038;p=279621"},"modified":"2023-04-15T14:47:44","modified_gmt":"2023-04-15T14:47:44","slug":"several-problems-were-found-when-using-the-siwavecircuit","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/several-problems-were-found-when-using-the-siwavecircuit\/","title":{"rendered":"Several problems were found when using the SIWAVE+circuit"},"content":{"rendered":"<p>Hello everyone,&nbsp;<br \/>I&#8217;ve been learning about SIWAVE and circuit recently. And I found three problems using Desktop Circuit and SIWAVE. I would be grateful if any experts had experienced similar problems and would be willing to help me.<br \/>1. I imported a design with bond wires into SIWAVE. After modifying the layer stackup, the circuit element part and draw geometry part could not be used.<img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/04\/15-04-2023-1681569851-1.png\" alt=\"\"><\/p>\n<p>2. I checked the connection of net A12 and there was no problem, but the following warning appeared when calculating SYZ parameters. This port uses the same reference as the other ports. What is the reason why these two ports were ignored?<img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/04\/15-04-2023-1681569864-2.png\" alt=\"\"> <img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/04\/15-04-2023-1681569879-3.png\" alt=\"\"><\/p>\n<p>3. I imported the S-parameters obtained from SIWAVE into NDE for passivity check and found that there was no problem, but there was a warning when it was used in Circuit. What is the reason?<img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/04\/15-04-2023-1681569888-4.png\" alt=\"\"><img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/04\/15-04-2023-1681569898-Snipaste_2023-04-15_21-52-31.png\" alt=\"\"><\/p>\n","protected":false},"template":"","class_list":["post-279621","topic","type-topic","status-closed","hentry","topic-tag-ansys-circuit","topic-tag-ansys-electronics-desktop","topic-tag-AnsysSiwave-1"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_author_ip":["96.7.74.173"],"_bbp_subscription":["281520","282636","277871","16577","159026"],"_btv_view_count":["2620"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["279621"],"_bbp_forum_id":["27793"],"_bbp_engagement":["16577","159026","281520"],"_bbp_voice_count":["3"],"_bbp_reply_count":["2"],"_bbp_reply_count_hidden":["2"],"_bbp_last_reply_id":["282883"],"_bbp_last_active_id":["282883"],"_bbp_last_active_time":["2023-05-08 18:50:43"]},"test":"wenbostu-xidian-edu-cn"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/279621","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/279621\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=279621"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}