{"id":249090,"date":"2023-02-08T10:33:51","date_gmt":"2023-02-08T10:33:51","guid":{"rendered":"\/forum\/forums\/topic\/modelling-mosfet-in-siwave-icepak-for-pcb-simulation\/"},"modified":"2023-02-08T11:24:21","modified_gmt":"2023-02-08T11:24:21","slug":"modelling-mosfet-in-siwave-icepak-for-pcb-simulation","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/modelling-mosfet-in-siwave-icepak-for-pcb-simulation\/","title":{"rendered":"Modelling MOSFET in SIwave\/Icepak for PCB simulation"},"content":{"rendered":"<p>Hello.&nbsp; I&#8217;m going to model a PCB layout for a three-phase inverter circuit.&nbsp; It&#8217;s a high current design and I&#8217;m mostly interested in simulating the DCIR drop in SIwave then doing the thermal analysis in Icepak.&nbsp; &nbsp;As a complete beginner, I have watched a few of the tutorials but I&#8217;m still struggling with the best way to represent the MOSFETs.&nbsp; See the attached generic picture of a similar circuit.<\/p>\n<p>I know I can designate a given power dissipation for each MOSFET in Icepak.&nbsp; But to model the effect of the PCB trace geometry I need a good representation of the DC current in the bridge section.&nbsp; &nbsp;What is the best method?&nbsp; Should I add a current source to each MOSFET drain terminal and a voltage source to each MOSFET source terminal?&nbsp;&nbsp;<\/p>\n<p>If anyone has done a similar analysis I would be very grateful for some tips.<\/p>\n<p>&nbsp;<\/p>\n<p>Many thanks<\/p>\n<p>Phil<\/p>\n<p>&nbsp;<\/p>\n<p><a class=\"wp-colorbox-image cboxElement\" href=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/02\/08-02-2023-1675851966-driver.png\"><img decoding=\"async\" src=\"\/forum\/wp-content\/uploads\/sites\/2\/2023\/02\/08-02-2023-1675851966-driver.png\" alt=\"\"><\/a><\/p>\n","protected":false},"template":"","class_list":["post-249090","topic","type-topic","status-closed","hentry","topic-tag-icepak","topic-tag-pcb","topic-tag-siwave"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_subscription":["274569","28551"],"_bbp_author_ip":["23.192.164.18"]," _bbp_last_reply_id":["0"]," _bbp_likes_count":["0"],"_btv_view_count":["1692"],"_edit_lock":["1675855384:205275"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["249090"],"_bbp_forum_id":["27793"],"_bbp_engagement":["28551","274569"],"_bbp_voice_count":["2"],"_bbp_reply_count":["2"],"_bbp_last_reply_id":["276577"],"_bbp_last_active_id":["276577"],"_bbp_last_active_time":["2023-03-27 11:57:54"]},"test":"pcollinsallegromicro-com"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/249090","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/249090\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=249090"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}