{"id":248844,"date":"2023-02-06T21:01:41","date_gmt":"2023-02-06T21:01:41","guid":{"rendered":"\/forum\/forums\/topic\/discrepancy-between-wall-clock-time-per-iteration-and-actual-time-per-iteration\/"},"modified":"2023-02-06T21:01:41","modified_gmt":"2023-02-06T21:01:41","slug":"discrepancy-between-wall-clock-time-per-iteration-and-actual-time-per-iteration","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/discrepancy-between-wall-clock-time-per-iteration-and-actual-time-per-iteration\/","title":{"rendered":"Discrepancy Between Wall Clock Time per Iteration and Actual Time per Iteration"},"content":{"rendered":"<p>I am working on a 2-phase flow simulation on an HPC cluster. The simplest case uses a single node with 24 cores and 8gb RAM per core (reserved the entire node). When I start the simulation I see a wall-clock time per iteration of around .017. Visually, the console shows quick residual printouts per iteration that matches this speed. However, over time this visual printout in the console slows down. When I check the Parallel -&gt; Usage tab I see roughly the same wall clock time per iteration. When I time it with a stop watch I get a completely different value (much higher). If I pause and re-start the simulation the console printouts appear to speed up again.&nbsp;<\/p>\n<p>What&#8217;s the issue here? I originially had monitors running every 100 iterations &#8211; I ran a test without monitors for some time and saw the same phenomenon. I have a workstation that I use and did not see any noticable visual slowdown in residual printouts in the console. Is there something to look out for when running on HPC that could cause this? Any insight would be helpful, thank you.&nbsp;<\/p>\n","protected":false},"template":"","class_list":["post-248844","topic","type-topic","status-closed","hentry"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_subscription":["192628","22555"],"_bbp_author_ip":["23.192.164.18"]," _bbp_last_reply_id":["0"]," _bbp_likes_count":["0"],"_btv_view_count":["1331"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["248844"],"_bbp_forum_id":["27792"],"_bbp_engagement":["22555","192628"],"_bbp_voice_count":["2"],"_bbp_reply_count":["5"],"_bbp_last_reply_id":["249333"],"_bbp_last_active_id":["249333"],"_bbp_last_active_time":["2023-02-10 07:08:51"]},"test":"rohan-tadepalligatech-edu"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/248844","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/248844\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=248844"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}