{"id":169351,"date":"2022-05-11T17:05:52","date_gmt":"2022-05-11T17:05:52","guid":{"rendered":"\/forum\/forums\/topic\/hfss-lumped-port-for-grounded-cpw\/"},"modified":"2022-05-16T07:12:40","modified_gmt":"2022-05-16T07:12:40","slug":"hfss-lumped-port-for-grounded-cpw","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/hfss-lumped-port-for-grounded-cpw\/","title":{"rendered":"HFSS lumped port for grounded CPW"},"content":{"rendered":"<div class=\"Item-Body\">\n<div class=\"Message userContent\">\n<p><\/p>\n<p>Hi,<\/p>\n<p>I am trying to simulate an antenna placed on a FR4 substrate (snapshot attached). PCB top and bottom layer are metal connected through VIAs. For this case, to assign a port, I have just drawn a rectangle at the edge of the PCB having a width same as the feedline and length same as the PCB height.<\/p>\n<p>Is it the correct way of assigning lumped port for my case ? If not, would you please tell how should I assign the port accurately?<\/p>\n<p><\/p>\n<\/p>\n<div class=\"embedExternal embedImage\">\n<div class=\"embedExternal-content\">\n<a class=\"embedImage-link\" href=\"\/forum\/wp-content\/uploads\/forum-uploads\/221\/0A5KRV2TW3DD.png\" rel=\"nofollow noopener\" target=\"_blank\"><br \/>\n<img decoding=\"async\" class=\"embedImage-img\" src=\"\/forum\/wp-content\/uploads\/forum-uploads\/221\/0A5KRV2TW3DD.png\" alt=\"Antenna_on_PCB.PNG\" \/><br \/>\n<\/a><\/p>\n","protected":false},"template":"","class_list":["post-169351","topic","type-topic","status-closed","hentry","topic-tag-antenna","topic-tag-hfss","topic-tag-lumped-ports","topic-tag-pcb","topic-tag-substrate-1"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_btv_view_count":["941"],"_bbp_likes_count":["0"],"_bbp_subscription":["40644"],"_bbpmt_movedon":["2022-07-01 16:11:19"],"_bbpmt_movedfrom":["151970"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["169351"],"_bbp_forum_id":["27793"],"_bbp_engagement":["195","40644"],"_bbp_voice_count":["2"],"_bbp_reply_count":["1"],"_bbp_last_reply_id":["214425"],"_bbp_last_active_id":["214425"],"_bbp_last_active_time":["2022-05-16 07:12:40"]},"test":"manjurul-riheenkyocera-avx-com"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/169351","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/169351\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=169351"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}