{"id":159620,"date":"2021-06-18T15:20:10","date_gmt":"2021-06-18T15:20:10","guid":{"rendered":"\/forum\/forums\/topic\/how-to-export-a-lib-spice-file-from-a-circuit-in-simplorer-circuit-2\/"},"modified":"2021-07-09T14:39:27","modified_gmt":"2021-07-09T14:39:27","slug":"how-to-export-a-lib-spice-file-from-a-circuit-in-simplorer-circuit-2","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/how-to-export-a-lib-spice-file-from-a-circuit-in-simplorer-circuit-2\/","title":{"rendered":"How to export a &#8216;.lib&#8217; (spice) file from a circuit in simplorer\/ circuit?"},"content":{"rendered":"<div class=\"Item-Body\">\n<div class=\"Message userContent\">\n<p>Hi all,<\/p>\n<p>I&#039;m modeling capacitors and the dielectric resistance is frequency dependent, which I can easily represent it through Ansys, putting directly the expression where frequency is a variable. <\/p>\n<p>This is good for me, by the way I need to export spice files like &#039;.lib&#039;, when we make the equivalent circuit in Q3D, I know that there is a tool that allow us to take spice files directly, but this is not the case. I&#039;m making the circuit directly in simplorer\/ circuit environment. <\/p>\n<p>I&#039;ve already tried to copy and translate the netlist to LTSpice, and there I would generate the lib files, but I&#039;ve not been successful until now.<\/p>\n<p>Which alternative do we got?<\/p>\n","protected":false},"template":"","class_list":["post-159620","topic","type-topic","status-closed","hentry","topic-tag-export","topic-tag-spice"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_author_ip":[""],"_bbp_old_reply_author_name_id":["Anonymous"],"_bbp_old_is_reply_anonymous_id":["false"],"_btv_view_count":["2004"],"_bbp_likes_count":["0"],"_bbp_subscription":["245110"],"_bbpmt_movedon":["2022-07-01 17:10:30"],"_bbpmt_movedfrom":["151970"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["159620"],"_bbp_forum_id":["27793"],"_bbp_engagement":["159026","204428"],"_bbp_voice_count":["2"],"_bbp_reply_count":["4"],"_bbp_last_reply_id":["182645"],"_bbp_last_active_id":["182645"],"_bbp_last_active_time":["2021-07-09 14:39:27"]},"test":"ruipardalkemet-com"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/159620","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/159620\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=159620"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}