{"id":158427,"date":"2021-05-12T16:08:44","date_gmt":"2021-05-12T16:08:44","guid":{"rendered":"\/forum\/forums\/topic\/what-are-the-correct-options-settings-for-exporting-a-pcb-layout-from-siwave-to-q3d\/"},"modified":"2021-05-20T14:15:06","modified_gmt":"2021-05-20T14:15:06","slug":"what-are-the-correct-options-settings-for-exporting-a-pcb-layout-from-siwave-to-q3d","status":"closed","type":"topic","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/topic\/what-are-the-correct-options-settings-for-exporting-a-pcb-layout-from-siwave-to-q3d\/","title":{"rendered":"What are the correct options\/settings for exporting a PCB layout from SIWAVE to Q3D?"},"content":{"rendered":"<div class=\"Item-Body\">\n<div class=\"Message userContent\">\n<p>The exported design in Q3D displays an air gap in between a via and adjacent copper plane. Could you please suggest some options with which there are no such flaws in the geometry? <\/p>\n<p>In the following figures I am displaying a flaw as well as all the options used for exporting the file to Q3D? The PCB was designed using Altium and imported into SIWAVE using &quot;Import ODB++&quot; option.<\/p>\n<div class=\"embedExternal embedImage\">\n<div class=\"embedExternal-content\">\n<a class=\"embedImage-link\" href=\"\/forum\/wp-content\/uploads\/forum-uploads\/910\/SDE2WBJTCKIU.png\" rel=\"nofollow noopener\" target=\"_blank\"><br \/>\n<img decoding=\"async\" class=\"embedImage-img\" src=\"\/forum\/wp-content\/uploads\/forum-uploads\/910\/SDE2WBJTCKIU.png\" alt=\"Overall Via.PNG\" \/><br \/>\n<\/a><\/p>\n","protected":false},"template":"","class_list":["post-158427","topic","type-topic","status-closed","hentry"],"aioseo_notices":[],"acf":[],"custom_fields":[{"0":{"_bbp_author_ip":[""],"_bbp_old_reply_author_name_id":["Anonymous"],"_bbp_old_is_reply_anonymous_id":["false"],"_btv_view_count":["963"],"_bbp_likes_count":["0"],"_bbp_subscription":["234472"],"_bbpmt_movedon":["2022-07-01 17:15:15"],"_bbpmt_movedfrom":["151970"],"_bbp_topic_status":["unanswered"],"_bbp_status":["publish"],"_bbp_topic_id":["158427"],"_bbp_forum_id":["27793"],"_bbp_engagement":["28551","189966"],"_bbp_voice_count":["2"],"_bbp_reply_count":["2"],"_bbp_last_reply_id":["178590"],"_bbp_last_active_id":["178590"],"_bbp_last_active_time":["2021-05-20 14:15:06"]},"test":"bsr"}],"_links":{"self":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/158427","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics"}],"about":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/types\/topic"}],"version-history":[{"count":0,"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/topics\/158427\/revisions"}],"wp:attachment":[{"href":"https:\/\/innovationspace.ansys.com\/forum\/wp-json\/wp\/v2\/media?parent=158427"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}