{"id":308450,"date":"2023-09-25T15:33:05","date_gmt":"2023-09-25T15:33:05","guid":{"rendered":"\/forum\/forums\/reply\/308450\/"},"modified":"2023-09-25T15:33:05","modified_gmt":"2023-09-25T15:33:05","slug":"308450","status":"publish","type":"reply","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/reply\/308450\/","title":{"rendered":"Reply To: Capacitance analysis of parallel plate capacitors in MAPDL"},"content":{"rendered":"

<p>Hi Yuuhi,<\/p><p>I’m sorry I don’t quite understand your question. The input file creates annotated images such as the one below. The first two lines of annotation report the MAPDL-calulated capacitance <span style=”text-decoration: underline;”>including fringing<\/em><\/span> deduced from results in two different ways. The third line reports the analytical fringe-free value, which is, as we expect, smaller. <\/p><p>Maybe I’m missing something, but I don’t see how you are using loop variable “i” to vary the size or separation of the plates. Are you asking how to vary the geometry in a do loop to investigate the effect of geometry on fringing and capacitance?<\/p><p>Or are you asking for an analytical expression that accounts for field fringing so that you can validate the calculated value from the finite element model? You might have to search the internet for that. I don’t think that this article is exactly what you want, but it might help give you an idea what kind of articles you might find if you look further:<\/p><p>(PDF) Effect of Fringing Fields on the Capacitance of Circular Microstrip Disk (researchgate.net)<\/a><\/p><p>Kind regards,<\/p><p>Bill<\/p><p> <\/p><p> <\/p><p> <\/p><\/p>\n","protected":false},"template":"","class_list":["post-308450","reply","type-reply","status-publish","hentry"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t