{"id":213390,"date":"2022-05-11T18:31:51","date_gmt":"2022-05-11T18:31:51","guid":{"rendered":"\/forum\/forums\/reply\/213390\/"},"modified":"2022-05-11T18:31:51","modified_gmt":"2022-05-11T18:31:51","slug":"213390","status":"publish","type":"reply","link":"https:\/\/innovationspace.ansys.com\/forum\/forums\/reply\/213390\/","title":{"rendered":"Reply To: Solving adaptive frequency …. process hf3d error: Failure in solving matrix. Please contact Ansys"},"content":{"rendered":"

1.
\n am using 30 passes but it shoots error even before reaching to the number I set. Also, as it looks very unstable, I am setting “minimum converged passes” to 2 rather than 1.<\/p>\n

2.
\nIt did not help.<\/p>\n

3.
\nI hope this schematic helps. I am designing a CPW line in a super thin substrate wafer (quartz). so T_Quartz is set around 10-20um. Accordingly, W and G must be set super small (sub-um) to meet our design goals.
\nThis is a screen capture from HFSS 2022R1.
\nthe yellow areas are all PEC boundaries as the thickness of conductors is very small too.<\/p>\n

It does not shoot error when “W” in the previous screen capture was large like more than 100um. However, we have to design a very narrow line for our applications.
\nIn the HFSS design screen capture the block at the center in the top screen capture was not included.<\/p>\n

4.
\nYes will do. but when I increased W and G, the problem never happens. I seems like due to very small mesh size required to simulate.
\nAny material useful for this problem?<\/p>\n","protected":false},"template":"","class_list":["post-213390","reply","type-reply","status-publish","hentry"],"aioseo_notices":[],"aioseo_head":"\n\t\t\n\t\n\t\n\t\n\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t\n\t\t