Reply To: Q3D Plane and Via Inductance Extraction

[Sriparna]

Hi,

Thanks for asking the question in Ansys Learning Forum.

Usually we do source and sink definition for PWR and GND net on both VRM and Microcontroller side in Q3D. So there will be one source and sink for PWR net and another source and sink for GND net. Then we can consider Return path Reduce matrix operation to evaluate Loop Inductance of the PWR plane. There we define the GND net as the Return path.