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Ansys Learning Forum › Forums › Discuss Simulation › Electronics › Validation error – where are the settings? › Reply To: Validation error – where are the settings?

August 27, 2024 at 5:31 am
dushyant.marathe
Ansys Employee
 Hi Tabea,
 
This error appears in Q3D during the Validations.
 
The possible cause of the error is if the SignalNet1 has unconnected conductors. The Net represents the logical connectivity defined in the schematics and may have signal traces, vias connected. Please consider this as an example. If there is slightest gap in the geometry for example if via is not touching to top traces even by um separation and even if one forms a net representing trace and via together. The above error appears in Q3D validations. To mitigate the error, make sure that every geometry which is a part of Net has electrical connectivity.
 
Thanks,

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