Reply To: Ansys Electronics Desktop – Circuits – Convolution for transient simulation

[Lucas Agustin Kammann]

Hi Dan, thanks for your reply.

 

The simulation fails in the “Loading devices…” stage, I believe it’s when it performs the state-space fitting as you say. It throws an error that says “memory allocation error”. I monitored the process with the Resources Monitor for Windows and it consumes over 100% of the available memory until it fails. I disabled the passivity enforcement in the DDRwizard because I read that it tends to use much more memory. The following image show the memory consumption:

Our design has 9 DDR3L SDRAMs operating at 1866Mbps. I need to analyze the compliance of the design with the JEDEC standard. So I extracted the S-parameters using the DDRwizard for the data buses of all the SDRAMs and the control signals (address, command, clock, etc). Then, I performed a transient simulation with the circuit created by the wizard to extract the waveforms so I could use the Compliance Toolkit to evaluate the compliance. The simulation fails because it runs out of memory when using the state-space representation, but it works with the convolution method. I compared both solutions when running it for only a single DDR3L SDRAM, and the results difference was negligible. Although the convolution method takes much more time to finish.

 

What do you think? I’d say that maybe there’s not much difference in the results obtained using the convolution method, and the only drawback in my particular case would be the simulation time (which is more or less 48 hours for the 9 SDRAMs).

 

Any advise is welcomed.

 

Thanks in advance.